International Electron Devices Meeting (IEDM) · 2026
Experimental Demonstration of a 2-Tier Monolithic 3D FeTFT Array with 3-b/cell Analog MAC and Full-Stack Evaluation for CNN and MoE-LLM Inference
Vertical stacking and heterogeneous integration for next-generation logic and memory, with a focus on thermal budget and interconnect parasitics.
More ViewNeuromorphic devices and synaptic arrays that emulate biological computation — visual receptive fields, olfaction, and spiking dynamics.
More ViewProbabilistic bits and Ising machines for combinatorial optimization, realized entirely in CMOS-compatible technology.
More ViewPhysics of device degradation — floating-body and self-heating effects, dielectric and interface reliability — across silicon and oxide semiconductors, from logic and DRAM to NAND, TFT, and capacitors.
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